A typical semiconductor design process includes numerous steps. Initially, a circuit designer prepares a schematic diagram that includes logical connections between logic elements that form an integrated circuit. The schematic diagram is then tested to verify that the logic elements and associated logical connections perform a desired function. Once the circuit is verified, the schematic diagram is converted into a mask layout database that includes a pattern of polygons. The polygons may represent the logic elements and the logical connections contained the schematic diagram. The mask layout database is then converted into multiple photomasks, also know as masks or reticles, that may be used to image different layers of the integrated circuit on to a semiconductor wafer.
Over the past several years, the number of transistors that form an integrated circuit has increased dramatically. As the number of transistors increase, the widths of the gates that form these transistors continue to decrease. During a fabrication process for an integrated circuit, various plasma etching and ion implantation techniques may be used, which may cause a charge to build up in a polysilicon gate. If the metal area to polysilicon gate ratio is low, the voltage buildup in the polysilicon gate may be tolerable. However, if the metal area is large compared to the polysilicon to which it is connected, there may be sufficient charge build up to degrade and even damage the polysilicon gate. This higher ratio of metal area to polysilicon gate is known as the antenna effect because the additional metal area acts like an antenna that collects charge.
The antenna effect may be reduced or eliminated by reducing the ratio of the metal area to the polysilicon gate area. Typically, a mask layout database may be analyzed either manually or automatically to determine regions where the antenna effect requires that the amount of metal be reduced. The areas affected by the antenna effect are then manually edited by a layout designer. The process of editing the layout database may be time consuming since the designer must create space for additional polygons, place the polygons in the mask layout database, and provide the appropriate electrical connections between the logic functions. During the placement and routing process, the layout designer may move polygons in order to provide a connection to the appropriate node. The layout designer may inadvertently create design rule violations or connectivity errors. The layout designer may then have to correct the violations and errors until the mask layout database is clean. The process of iteratively correcting the design rule violations may take several hours or even days to complete and can increase the time needed to design the integrated circuit. The additional time required to complete layout may also delay the production of a photomask set used to fabricate the integrated circuit.